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altsyncram_4ps1.tdf
Package: inter_prediction(verilog).rar　[view]
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Upload Date: 2020-10-12
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Compress-Decompress algrithms

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VHDL

altsyncram_4ps1.tdf：Code Content
  1. --altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone II" INIT_FILE="cb1.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=16 NUMWORDS_B=16 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="CLOCK0" POWER_UP_UNINITIALIZED="FALSE" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=4 WIDTHAD_B=4 address_a address_b clock0 data_a q_b rden_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
  2. --VERSION_BEGIN 7.1 cbx_altsyncram 2007:03:22:08:29:24:SJ cbx_cycloneii 2007:01:23:09:39:40:SJ cbx_lpm_add_sub 2007:01:08:11:15:18:SJ cbx_lpm_compare 2007:02:05:11:33:54:SJ cbx_lpm_decode 2006:11:21:10:27:00:SJ cbx_lpm_mux 2006:11:21:10:27:10:SJ cbx_mgl 2007:04:03:14:06:46:SJ cbx_stratix 2007:04:12:16:43:52:SJ cbx_stratixii 2007:02:12:17:08:26:SJ cbx_stratixiii 2007:03:13:14:47:12:SJ cbx_util_mgl 2007:01:15:12:22:48:SJ  VERSION_END
  5. -- Copyright (C) 1991-2007 Altera Corporation
  6. --  Your use of Altera Corporation's design tools, logic functions 
  7. --  and other software and tools, and its AMPP partner logic 
  8. --  functions, and any output files from any of the foregoing 
  9. --  (including device programming or simulation files), and any 
  10. --  associated documentation or information are expressly subject 
  11. --  to the terms and conditions of the Altera Program License 
  12. --  Subscription Agreement, Altera MegaCore Function License 
  13. --  Agreement, or other applicable license agreement, including, 
  14. --  without limitation, that your use is for the sole purpose of 
  15. --  programming logic devices manufactured by Altera and sold by 
  16. --  Altera or its authorized distributors.  Please refer to the 
  17. --  applicable agreement for further details.
  20. PARAMETERS
  21. (
  22. PORT_A_ADDRESS_WIDTH = 1,
  23. PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
  24. PORT_A_DATA_WIDTH = 1,
  25. PORT_B_ADDRESS_WIDTH = 1,
  26. PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
  27. PORT_B_DATA_WIDTH = 1
  28. );
  29. FUNCTION cycloneii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe)
  30. WITH (  CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_WIDTH, PORT_A_BYTE_ENABLE_MASK_WIDTH, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS, PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS, PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE) 
  31. RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
  33. --synthesis_resources = M4K 1 
  34. OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
  36. SUBDESIGN altsyncram_4ps1
  37. ( 
  38. address_a[3..0] : input;
  39. address_b[3..0] : input;
  40. clock0 : input;
  41. data_a[7..0] : input;
  42. q_b[7..0] : output;
  43. rden_b : input;
  44. wren_a : input;
  45. ) 
  46. VARIABLE 
  47. ram_block1a0 : cycloneii_ram_block
  48. WITH (
  49. CONNECTIVITY_CHECKING = "OFF",
  50. DONT_POWER_OPTIMIZE = "ON",
  51. INIT_FILE = "cb1.mif",
  52. INIT_FILE_LAYOUT = "port_b",
  53. LOGICAL_RAM_NAME = "ALTSYNCRAM",
  54. MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
  55. OPERATION_MODE = "dual_port",
  56. PORT_A_ADDRESS_WIDTH = 4,
  57. PORT_A_DATA_WIDTH = 1,
  58. PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
  59. PORT_A_FIRST_ADDRESS = 0,
  60. PORT_A_FIRST_BIT_NUMBER = 0,
  61. PORT_A_LAST_ADDRESS = 15,
  62. PORT_A_LOGICAL_RAM_DEPTH = 16,
  63. PORT_A_LOGICAL_RAM_WIDTH = 8,
  64. PORT_B_ADDRESS_CLOCK = "clock0",
  65. PORT_B_ADDRESS_WIDTH = 4,
  66. PORT_B_DATA_OUT_CLEAR = "none",
  67. PORT_B_DATA_OUT_CLOCK = "clock0",
  68. PORT_B_DATA_WIDTH = 1,
  69. PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
  70. PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
  71. PORT_B_FIRST_ADDRESS = 0,
  72. PORT_B_FIRST_BIT_NUMBER = 0,
  73. PORT_B_LAST_ADDRESS = 15,
  74. PORT_B_LOGICAL_RAM_DEPTH = 16,
  75. PORT_B_LOGICAL_RAM_WIDTH = 8,
  76. PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
  77. POWER_UP_UNINITIALIZED = "false",
  78. RAM_BLOCK_TYPE = "AUTO"
  79. );
  80. ram_block1a1 : cycloneii_ram_block
  81. WITH (
  82. CONNECTIVITY_CHECKING = "OFF",
  83. DONT_POWER_OPTIMIZE = "ON",
  84. INIT_FILE = "cb1.mif",
  85. INIT_FILE_LAYOUT = "port_b",
  86. LOGICAL_RAM_NAME = "ALTSYNCRAM",
  87. MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
  88. OPERATION_MODE = "dual_port",
  89. PORT_A_ADDRESS_WIDTH = 4,
  90. PORT_A_DATA_WIDTH = 1,
  91. PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
  92. PORT_A_FIRST_ADDRESS = 0,
  93. PORT_A_FIRST_BIT_NUMBER = 1,
  94. PORT_A_LAST_ADDRESS = 15,
  95. PORT_A_LOGICAL_RAM_DEPTH = 16,
  96. PORT_A_LOGICAL_RAM_WIDTH = 8,
  97. PORT_B_ADDRESS_CLOCK = "clock0",
  98. PORT_B_ADDRESS_WIDTH = 4,
  99. PORT_B_DATA_OUT_CLEAR = "none",
  100. PORT_B_DATA_OUT_CLOCK = "clock0",
  101. PORT_B_DATA_WIDTH = 1,
  102. PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
  103. PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
  104. PORT_B_FIRST_ADDRESS = 0,
  105. PORT_B_FIRST_BIT_NUMBER = 1,
  106. PORT_B_LAST_ADDRESS = 15,
  107. PORT_B_LOGICAL_RAM_DEPTH = 16,
  108. PORT_B_LOGICAL_RAM_WIDTH = 8,
  109. PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
  110. POWER_UP_UNINITIALIZED = "false",
  111. RAM_BLOCK_TYPE = "AUTO"
  112. );
  113. ram_block1a2 : cycloneii_ram_block
  114. WITH (
  115. CONNECTIVITY_CHECKING = "OFF",
  116. DONT_POWER_OPTIMIZE = "ON",
  117. INIT_FILE = "cb1.mif",
  118. INIT_FILE_LAYOUT = "port_b",
  119. LOGICAL_RAM_NAME = "ALTSYNCRAM",
  120. MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
  121. OPERATION_MODE = "dual_port",
  122. PORT_A_ADDRESS_WIDTH = 4,
  123. PORT_A_DATA_WIDTH = 1,
  124. PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
  125. PORT_A_FIRST_ADDRESS = 0,
  126. PORT_A_FIRST_BIT_NUMBER = 2,
  127. PORT_A_LAST_ADDRESS = 15,
  128. PORT_A_LOGICAL_RAM_DEPTH = 16,
  129. PORT_A_LOGICAL_RAM_WIDTH = 8,
  130. PORT_B_ADDRESS_CLOCK = "clock0",
  131. PORT_B_ADDRESS_WIDTH = 4,
  132. PORT_B_DATA_OUT_CLEAR = "none",
  133. PORT_B_DATA_OUT_CLOCK = "clock0",
  134. PORT_B_DATA_WIDTH = 1,
  135. PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
  136. PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
  137. PORT_B_FIRST_ADDRESS = 0,
  138. PORT_B_FIRST_BIT_NUMBER = 2,
  139. PORT_B_LAST_ADDRESS = 15,
  140. PORT_B_LOGICAL_RAM_DEPTH = 16,
  141. PORT_B_LOGICAL_RAM_WIDTH = 8,
  142. PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
  143. POWER_UP_UNINITIALIZED = "false",
  144. RAM_BLOCK_TYPE = "AUTO"
  145. );
  146. ram_block1a3 : cycloneii_ram_block
  147. WITH (
  148. CONNECTIVITY_CHECKING = "OFF",
  149. DONT_POWER_OPTIMIZE = "ON",
  150. INIT_FILE = "cb1.mif",
  151. INIT_FILE_LAYOUT = "port_b",
  152. LOGICAL_RAM_NAME = "ALTSYNCRAM",
  153. MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
  154. OPERATION_MODE = "dual_port",
  155. PORT_A_ADDRESS_WIDTH = 4,
  156. PORT_A_DATA_WIDTH = 1,
  157. PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
  158. PORT_A_FIRST_ADDRESS = 0,
  159. PORT_A_FIRST_BIT_NUMBER = 3,
  160. PORT_A_LAST_ADDRESS = 15,
  161. PORT_A_LOGICAL_RAM_DEPTH = 16,
  162. PORT_A_LOGICAL_RAM_WIDTH = 8,
  163. PORT_B_ADDRESS_CLOCK = "clock0",
  164. PORT_B_ADDRESS_WIDTH = 4,
  165. PORT_B_DATA_OUT_CLEAR = "none",
  166. PORT_B_DATA_OUT_CLOCK = "clock0",
  167. PORT_B_DATA_WIDTH = 1,
  168. PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
  169. PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
  170. PORT_B_FIRST_ADDRESS = 0,
  171. PORT_B_FIRST_BIT_NUMBER = 3,
  172. PORT_B_LAST_ADDRESS = 15,
  173. PORT_B_LOGICAL_RAM_DEPTH = 16,
  174. PORT_B_LOGICAL_RAM_WIDTH = 8,
  175. PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
  176. POWER_UP_UNINITIALIZED = "false",
  177. RAM_BLOCK_TYPE = "AUTO"
  178. );
  179. ram_block1a4 : cycloneii_ram_block
  180. WITH (
  181. CONNECTIVITY_CHECKING = "OFF",
  182. DONT_POWER_OPTIMIZE = "ON",
  183. INIT_FILE = "cb1.mif",
  184. INIT_FILE_LAYOUT = "port_b",
  185. LOGICAL_RAM_NAME = "ALTSYNCRAM",
  186. MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
  187. OPERATION_MODE = "dual_port",
  188. PORT_A_ADDRESS_WIDTH = 4,
  189. PORT_A_DATA_WIDTH = 1,
  190. PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
  191. PORT_A_FIRST_ADDRESS = 0,
  192. PORT_A_FIRST_BIT_NUMBER = 4,
  193. PORT_A_LAST_ADDRESS = 15,
  194. PORT_A_LOGICAL_RAM_DEPTH = 16,
  195. PORT_A_LOGICAL_RAM_WIDTH = 8,
  196. PORT_B_ADDRESS_CLOCK = "clock0",
  197. PORT_B_ADDRESS_WIDTH = 4,
  198. PORT_B_DATA_OUT_CLEAR = "none",
  199. PORT_B_DATA_OUT_CLOCK = "clock0",
  200. PORT_B_DATA_WIDTH = 1,
  201. PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
  202. PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
  203. PORT_B_FIRST_ADDRESS = 0,
  204. PORT_B_FIRST_BIT_NUMBER = 4,
  205. PORT_B_LAST_ADDRESS = 15,
  206. PORT_B_LOGICAL_RAM_DEPTH = 16,
  207. PORT_B_LOGICAL_RAM_WIDTH = 8,
  208. PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
  209. POWER_UP_UNINITIALIZED = "false",
  210. RAM_BLOCK_TYPE = "AUTO"
  211. );
  212. ram_block1a5 : cycloneii_ram_block
  213. WITH (
  214. CONNECTIVITY_CHECKING = "OFF",
  215. DONT_POWER_OPTIMIZE = "ON",
  216. INIT_FILE = "cb1.mif",
  217. INIT_FILE_LAYOUT = "port_b",
  218. LOGICAL_RAM_NAME = "ALTSYNCRAM",
  219. MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
  220. OPERATION_MODE = "dual_port",
  221. PORT_A_ADDRESS_WIDTH = 4,
  222. PORT_A_DATA_WIDTH = 1,
  223. PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
  224. PORT_A_FIRST_ADDRESS = 0,
  225. PORT_A_FIRST_BIT_NUMBER = 5,
  226. PORT_A_LAST_ADDRESS = 15,
  227. PORT_A_LOGICAL_RAM_DEPTH = 16,
  228. PORT_A_LOGICAL_RAM_WIDTH = 8,
  229. PORT_B_ADDRESS_CLOCK = "clock0",
  230. PORT_B_ADDRESS_WIDTH = 4,
  231. PORT_B_DATA_OUT_CLEAR = "none",
  232. PORT_B_DATA_OUT_CLOCK = "clock0",
  233. PORT_B_DATA_WIDTH = 1,
  234. PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
  235. PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
  236. PORT_B_FIRST_ADDRESS = 0,
  237. PORT_B_FIRST_BIT_NUMBER = 5,
  238. PORT_B_LAST_ADDRESS = 15,
  239. PORT_B_LOGICAL_RAM_DEPTH = 16,
  240. PORT_B_LOGICAL_RAM_WIDTH = 8,
  241. PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
  242. POWER_UP_UNINITIALIZED = "false",
  243. RAM_BLOCK_TYPE = "AUTO"
  244. );
  245. ram_block1a6 : cycloneii_ram_block
  246. WITH (
  247. CONNECTIVITY_CHECKING = "OFF",
  248. DONT_POWER_OPTIMIZE = "ON",
  249. INIT_FILE = "cb1.mif",
  250. INIT_FILE_LAYOUT = "port_b",
  251. LOGICAL_RAM_NAME = "ALTSYNCRAM",
  252. MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
  253. OPERATION_MODE = "dual_port",
  254. PORT_A_ADDRESS_WIDTH = 4,
  255. PORT_A_DATA_WIDTH = 1,
  256. PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
  257. PORT_A_FIRST_ADDRESS = 0,
  258. PORT_A_FIRST_BIT_NUMBER = 6,
  259. PORT_A_LAST_ADDRESS = 15,
  260. PORT_A_LOGICAL_RAM_DEPTH = 16,
  261. PORT_A_LOGICAL_RAM_WIDTH = 8,
  262. PORT_B_ADDRESS_CLOCK = "clock0",
  263. PORT_B_ADDRESS_WIDTH = 4,
  264. PORT_B_DATA_OUT_CLEAR = "none",
  265. PORT_B_DATA_OUT_CLOCK = "clock0",
  266. PORT_B_DATA_WIDTH = 1,
  267. PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
  268. PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
  269. PORT_B_FIRST_ADDRESS = 0,
  270. PORT_B_FIRST_BIT_NUMBER = 6,
  271. PORT_B_LAST_ADDRESS = 15,
  272. PORT_B_LOGICAL_RAM_DEPTH = 16,
  273. PORT_B_LOGICAL_RAM_WIDTH = 8,
  274. PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
  275. POWER_UP_UNINITIALIZED = "false",
  276. RAM_BLOCK_TYPE = "AUTO"
  277. );
  278. ram_block1a7 : cycloneii_ram_block
  279. WITH (
  280. CONNECTIVITY_CHECKING = "OFF",
  281. DONT_POWER_OPTIMIZE = "ON",
  282. INIT_FILE = "cb1.mif",
  283. INIT_FILE_LAYOUT = "port_b",
  284. LOGICAL_RAM_NAME = "ALTSYNCRAM",
  285. MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
  286. OPERATION_MODE = "dual_port",
  287. PORT_A_ADDRESS_WIDTH = 4,
  288. PORT_A_DATA_WIDTH = 1,
  289. PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
  290. PORT_A_FIRST_ADDRESS = 0,
  291. PORT_A_FIRST_BIT_NUMBER = 7,
  292. PORT_A_LAST_ADDRESS = 15,
  293. PORT_A_LOGICAL_RAM_DEPTH = 16,
  294. PORT_A_LOGICAL_RAM_WIDTH = 8,
  295. PORT_B_ADDRESS_CLOCK = "clock0",
  296. PORT_B_ADDRESS_WIDTH = 4,
  297. PORT_B_DATA_OUT_CLEAR = "none",
  298. PORT_B_DATA_OUT_CLOCK = "clock0",
  299. PORT_B_DATA_WIDTH = 1,
  300. PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
  301. PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
  302. PORT_B_FIRST_ADDRESS = 0,
  303. PORT_B_FIRST_BIT_NUMBER = 7,
  304. PORT_B_LAST_ADDRESS = 15,
  305. PORT_B_LOGICAL_RAM_DEPTH = 16,
  306. PORT_B_LOGICAL_RAM_WIDTH = 8,
  307. PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
  308. POWER_UP_UNINITIALIZED = "false",
  309. RAM_BLOCK_TYPE = "AUTO"
  310. );
  311. address_a_wire[3..0] : WIRE;
  312. address_b_wire[3..0] : WIRE;
  314. BEGIN 
  315. ram_block1a[7..0].clk0 = clock0;
  316. ram_block1a[7..0].portaaddr[] = ( address_a_wire[3..0]);
  317. ram_block1a[0].portadatain[] = ( data_a[0..0]);
  318. ram_block1a[1].portadatain[] = ( data_a[1..1]);
  319. ram_block1a[2].portadatain[] = ( data_a[2..2]);
  320. ram_block1a[3].portadatain[] = ( data_a[3..3]);
  321. ram_block1a[4].portadatain[] = ( data_a[4..4]);
  322. ram_block1a[5].portadatain[] = ( data_a[5..5]);
  323. ram_block1a[6].portadatain[] = ( data_a[6..6]);
  324. ram_block1a[7].portadatain[] = ( data_a[7..7]);
  325. ram_block1a[7..0].portawe = wren_a;
  326. ram_block1a[7..0].portbaddr[] = ( address_b_wire[3..0]);
  327. ram_block1a[7..0].portbrewe = rden_b;
  328. address_a_wire[] = address_a[];
  329. address_b_wire[] = address_b[];
  330. q_b[] = ( ram_block1a[7..0].portbdataout[0..0]);
  331. END;
  332. --VALID FILE