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half_adder_1.v

Package: verilog.HDL.examples.rar　[view]

Upload User: saul_905

Upload Date: 2013-11-27

Package Size: 184k

Code Size: 0k

Category:

VHDL-FPGA-Verilog

Development Platform:

Visual C++

half_adder_1.v：Code Content

							module half_adder(a,b,out,carry);
input a,b;
output out,carry;
assign {carry,out}=a+b;
endmodule

						