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COMPARE.V

Package: verilog.HDL.examples.rar　[view]

Upload User: saul_905

Upload Date: 2013-11-27

Package Size: 184k

Code Size: 0k

Category:

VHDL-FPGA-Verilog

Development Platform:

Visual C++

COMPARE.V：Code Content

							module compare(a,b,equal);
parameter size=1;
input [size-1:0]a,b;
output equal;
assign  equal=(a==b)?1:0;
endmodule

						