Home > SourceCode/Document > Embeded-SCM Develop > VHDL-FPGA-Verilog > View Code

half_adder_3.v

Package: verilog.HDL.examples.rar　[view]

Upload User: saul_905

Upload Date: 2013-11-27

Package Size: 184k

Code Size: 0k

Category:

VHDL-FPGA-Verilog

Development Platform:

Visual C++

half_adder_3.v：Code Content

							module half_adder(a,b,out,carry);
input a,b;
output out,carry;
xor n1(out,a,b);
and n2(carry,a,b);
endmodule

						