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  • [VHDL] huffman.rar The huffman algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
    Category: VHDL-FPGA-Verilog Upload User:hylc_2004 Size:11K
  • [VHDL] quant.rar Quantitative algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
    Category: VHDL-FPGA-Verilog Upload User:taisight Size:14K
  • [VHDL] iquant.rar FPGA used to quantify anti-HDL coding algorithms, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
    Category: VHDL-FPGA-Verilog Upload User:dong2853 Size:13K
  • [VHDL] ethernet_tri_mode.tar.gz Using FPGA verilog hdl realize Gigabit Ethernet MAC.
    Category: VHDL-FPGA-Verilog Upload User:waytide Size:723K
  • [VHDL] IIC_Verilog.rar FPGA Verilog HDL IIC Interface
    Category: VHDL-FPGA-Verilog Upload User:szzhdy888 Size:200K
  • [VHDL] DCT.rar altera fpga verilog design table DCT-based search procedures and zigzag scanning procedures, and ModelSim matlab has been verified, the document contains TESTBENCH, directly available
    Category: VHDL-FPGA-Verilog Upload User:ziqing_518 Size:15040K
  • [VHDL] asynch_fifo.rar FPGA VERILOG using DCFIFO realize cross-clock domain data transfer, has been verified, directly available
    Category: VHDL-FPGA-Verilog Upload User:laitian922 Size:1004K
  • [VHDL] an_dcfifo_top_restored.rar alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.
    Category: VHDL-FPGA-Verilog Upload User:zhouhu188 Size:907K
  • [VHDL] dds.rar Based on VHDL+ FPGA design of the DDS signal has been through mode
    Category: VHDL-FPGA-Verilog Upload User:billow188 Size:547K
  • [VHDL] ethernet.tar.gz Ethernet VHDL and Verilog code for everyone to learn
    Category: VHDL-FPGA-Verilog Upload User:szhszm Size:913K